What is Data Layout

Mapping from logical indices to the phyiscal location of the data

or different devices...

Shape–Stride Model

We will use this notation:

Tile Layout

Representing tiling

Named Axes in Strides

We need to represent different hardware axese:

• Lane and col dimension in tensor memory
• Thread indcies

It is useful to have named axes, we use @m for normal meory

• Row-major 8×16: S[(8, 16) : (16@m, 1@m)]

The @axis tag can also be other things like @warpid, or @tmemcol

Distributed Axes: @gpuid_y, @gpuid_x

Representing broadcast / replication

Background: Memory Banks

Different memory banks can be read out in parallel

Swizzle as a Memory Optimization

Swizzle is an implicit remapping the hardware applies — just enable it

• Pass pre-swizzled addresses and use a consistent swizzle mode (e.g. SWIZZLE_128B) across ops
• Don't worry about swizzle yourself — let hardware handles it.
• Benefit: SWIZZLE_128B → conflict-free access to 8 rows and 8 columns at a time (fp16)

Swizzle is fundamentally a way to enable efficient column access — the idea is not specific to GPU shared memory!